0

I have an LCD interface for a Beaglebone Black that is failing EMC. The Pixel clock is 65 MHz and is failing there as well as 195 MHz. Here is what the schematic looks like:

enter image description here

The setup is 24 bits RGB that is converted to LVDS, which there are 4 lanes of data and the differential clock. I found the input LCD clock from the beaglebone to the LVDS transmitter was the worst, especially at 195 MHz. I greatly reduced the EMI by putting in a LC filter (BLM21BB201SN1D with a 22 pF Cap). Here is what it looked like before (195 MHz at center):

enter image description here

After:

enter image description here

The clock integrity was unaffected and this likely would be enough to pass. However, there is still a lot of ringing on the LVDS clock side and I would like to improve it. I tried putting in the same LC filter for the clock but it just impeded the clock too much. I was thinking of adding a common mode filter between the + and – clock but not sure that is the best way filter it. Any thoughts on how to do this would be appreciated.

Edit 1: Adding pictures of layout

enter image description here

enter image description here

enter image description here

enter image description here