I’m new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was successful. But even after that my work library is empty.
I don’t know what changed, as previously I followed the similar procedure and files were added in work directory. Is this some problem of path/logical mapping?
I tried reinstalling the software, but the problem is the same. The following is the image after successful compilation of the software: