I’ve implemented a division algorithm on an FPGA using the long division algorithm. My implementation does not use pipelining, but works iteratively and requires very few logic elements since the algorithm mainly consists of a single subtraction and some shift registers.

For a signed version of the component I just use the absolute values of the inputs and negate the result as required. This works as expected, but negating two’s complement numbers does require adding ‘1’ after inverting all bits, which results in 3 full adders in the design. This results in roughly twice as many logic elements for a signed divider compared to an unsigned one.

Is there a way to adjust the long division algorithm, so it directly works with negative numbers? I’ve already figured out that I can include the ‘+1’ for the denominator during the main subtraction by using a borrow bit. I haven’t found out how to handle the numerator or how to directly produce a result with the correct sign.